The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2001
Filed:
Oct. 05, 1998
Manouchehr Vafai, Los Gatos, CA (US);
Michael D. Rostoker, Boulder Creek, CA (US);
Kawasaki Steel Corporation, Tokyo, JP;
Abstract
Method and apparatus for significantly improving the reliability of multilevel (MLT) memory architecture. Before writing to MLT architecture, each MLT word is encoded into a coded bit stream in such a way that the resultant coded data contains the original word plus additional digits which are a function of the content of memory. During the reading of the memory, the stored data is decoded, and takes advantage of redundancy to correct and eliminate errors introduced during read and write operations of the MLT architecture. The invention is useful for systems such as general-purpose computers (PCs, workstations, etc.), telecommunications devices (telephones—wired and wireless, switches, hubs, routers, etc.), audio and visual devices (recording and playback, editing, format switching, compression, etc.), vehicles (automobiles, aircraft, trains, boats, satellites, spacecraft, etc.). Systems and subsystems may be incorporated on a single integrated circuit (IC) die having MLT RAM or enhanced MLT memory. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.