The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2001

Filed:

Nov. 29, 1999
Applicant:
Inventors:

John W. Cassen, Sykesville, MD (US);

Edward L. Rich, III, Arnold, MD (US);

Gary N. Bonadies, Laurel, MD (US);

John S. Fisher, Ellicott City, MD (US);

John W. Gipprich, Millersville, MD (US);

John D. Gornto, Columbia, MD (US);

Daniel J. Heffernan, Pasadena, MD (US);

David A. Herlihy, Ellicott City, MD (US);

Scott C. Tolle, Baltimore, MD (US);

Patrick K. Richard, Baltimore, MD (US);

David W. Strack, Baltimore, MD (US);

Scott K. Suko, Elkridge, MD (US);

Timothy L. Eder, Glen Burnie, MD (US);

Chad E. Wilson, Redmond, WA (US);

Gary L. Ferrell, Pasadena, MD (US);

Stephanie A. Parks, Virginia Beach, VA (US);

Assignee:

Northrop Grumman Corporation, Los Angeles, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 7/28 ;
U.S. Cl.
CPC ...
G01S 7/28 ;
Abstract

Two discrete transmit/receive (T/R) channels are implemented in a single common T/R module package having the capability of providing combined functions, control and power conditioning while utilizing a single multi-cavity, multi-layer substrate comprised of high or low temperature cofired ceramic layers. The ceramic layers have outer surfaces including respective metallization patterns of ground planes and stripline conductors as well as feedthroughs or vertical vias formed therein for providing three dimensional routing of both shielded RF and DC power and logic control signals so as to configure, among other things, a pair of RF manifold signal couplers which are embedded in the substrate and which transition to a multi-pin blind mate press-on RF connector assembly at the front end of the package. DC and logic input/output control signals are connected to a plurality of active circuit components including application specific integrated circuits (ASICs) and monolithic microwave integrated circuit chips (MMICs) via spring contact pads at the rear of the package. An RF connector assembly for coupling transmit and receive signals to and from the module is located at the front of the package. The RF transmit power amplifiers which generate most of the heat in the module package are located in a first pair of cavities formed in the substrate directly behind the RF connector assembly and are mounted directly on a pair of flat heat sink plates which are secured to the bottom of the substrate and acts as a thermal interface to an external heat exchanger such as a cold plate. A second pair of cavities in which are located the RF receive signal amplifiers and their respective receiver protector elements, is located beside the first pair of cavities directly behind the RF connector for reducing RF signal loss.


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