The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2001

Filed:

Apr. 28, 1998
Applicant:
Inventors:

Kiyoshi Mizushima, Matto, JP;

Makoto Aoki, Matto, JP;

Satoshi Ikeda, Matto, JP;

Noriyuki Tanagi, Matto, JP;

Assignee:

Nikko Company, Ishikawa-ken, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/312 ;
U.S. Cl.
CPC ...
H01L 2/312 ;
Abstract

A ball-grid-array-type semiconductor device comprising a package substrate constituted with a ceramic wiring board having a semiconductor chip mounting portion on the principal plane and electrodes arranged like an array on the back, a semiconductor chip secured to the principal plane of the package substrate, connection means for electrically connecting the electrodes of the semiconductor chip with the wiring of the wiring board, a sealing body provided for the principal plane side of the wiring board and made of an insulating resin to cover the semiconductor chip and the connection means, a pedestal layer made of low-fusion-point solder and formed on the electrodes, and a metallic ball secured onto the pedestal layer; wherein a buffering layer made of high-fusion-point solder which covers the entire surface of the electrodes and whose margin extends up to a predetermined length on the back of the package substrate is formed on the electrodes and the pedestal layer is formed on the buffering layer.


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