The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2001
Filed:
Aug. 25, 1999
George R. Misium, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A mixed voltage CMOS process for fabricating transistors with different source-drain profiles is described. The present invention comprises a method for manufacturing a CMOS integrated circuit with a low voltage device,and a high voltage device,comprising the steps of obtaining active regions in a substrate,with gates,and,for the low voltage device,and the high voltage device,, respectively, obtaining lightly implanted source and drain extensions,and,for the low voltage device,, forming a side wall,and,next to each gate,and,, and angularly implanting each of the source and drain regions,and,with an impurity,of a selected type for both the low voltage device,and the high voltage device,, to eliminate the need for separately implanting the first voltage device and second voltage device with different source-drain extensions. The method of the present invention tailors the source-drain implant conditions (energy, dose, angle,, and thermal drive) to create the source-drain profiles of a reliable high voltage device,without degrading the performance of the low voltage device