The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Sep. 30, 1997
Harold J. Levy, Cupertino, CA (US);
Subhas Bothra, San Jose, CA (US);
David C. Chapman, Santa Clara, CA (US);
Philips Electronics North America Corporation, New York, NY (US);
Abstract
Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientation to produce a first shifted via geometry. Performing a logical AND between the first shifted via geometry and the metallization geometry. The method further includes determining whether the logical AND produces a value indicative of a sufficient overlap between the identified metallization geometry and the first shifted via geometry.