Test circuit and a redundancy circuit for an internal memory circuit

Abstract

In the first test mode with a shift-mode signal (SM) of “1” and a test-mode signal (TM) of “1”, supplying a comparison control signal (CMP) of “1” makes a test-valid condition. Then, a comparison result between input data (D) which becomes “0” to indicate a failure and an expected value data (EXP) (an output of a comparator (,)) and an AND-operation result between a serial input (SI) and a latch data (an output of a D-FF (,)) are given to the D-FF (,) through NAND gates (,and,), an AND gate (,) and a selector (,). With this configuration achieved is a semiconductor integrated circuit having a test circuit which allows a quick recognition of whether there is a failure or not in an internal memory circuit under test.