Method and circuit for implementing digital delay lines using delay caches

Abstract

A circuit for implementing digital delay lines that includes a main memory, a cache memory, and a processor. The main memory implements at least one digital delay line, as many delay lines as required by a digital signal processing (DSP) program running on the processor, up to a predetermined number. The delay lines contain data samples to be operated on, or produced by DSP program. The cache memory implements a number of delay caches that temporarily store data samples and support the delay lines. Each delay line is associated with a read cache and a write cache. A block of data samples are “pre-fetched” from a delay line in the main memory and provided to the associated read cache. The data samples in the read cache are then accessed, as needed, by the processor. Data samples generated by the DSP program are provided to the write cache. Periodically, a block of data samples is “post-written” from the write cache to its corresponding delay line in the main memory. The delay caches are serviced such that the read caches do not underflow and the write caches do not overflow, thereby effectively “anticipating” data accesses by the processor. In one embodiment of the delay line circuit, each of the delay lines includes a circular buffer. In another embodiment, each of the delay caches has a cache size that is greater than the data transfer size. In yet another embodiment, each delay cache is selected for servicing approximately once every servicing period, wherein the servicing period is approximately B sample periods or less and uses a servicing scheme such as a round robin scheme or a priority scheme.