Contention-free signaling scheme for shared control signals

Abstract

A contention-free transition-based signaling scheme in which a plurality of controlling units and one or more controlled units are connected to a shared bus line, which is also connected to a bus holder cell. Each of the controlling units includes an output circuit that asserts a control signal on the bus line by synchronously asserting a logic level transition on the bus line, and each of the controlled units includes an input circuit that detects assertion of the control signal by detecting that a logic level transition has occurred on the bus line. The synchronous nature of the scheme avoids the possibility of contention because all of the controlling units that intend to assert a logic level transition in a given clock cycle sampled the current logic level at the same time (within the same prior clock cycle). They therefore all agree on the current logic level and will all assert the same opposite logic level when asserting their logic level transition. In addition, detection by the controlled unit input circuits of logic level transitions can be made synchronous as well.