Method of and system for processing datagram headers for high speed computer network interfaces at low clock speeds, utilizing scalable algorithms for performing such network header adaptation (sapna)

Abstract

A technique and system for manipulating, converting or adapting datagram headers as required during traverse from one interface of a networking device to another, by novel clocked micro-sequencing and selection amongst input and output FIFO data streams, through dividing input serial data streams into small groups of FIFO input data streams and feeding the groups parallely into a matrix of a multilane highway of header unit input data, constant data pattern and computational unit busses controlled by such micro-sequencing so as to enable such processing of packet datagram headers and the like at very high wire speed, but using low clock speeds, and in a scalable manner.