Programmable architecture fast packet switch

Abstract

A programmable fast packet switch testbed (,) for use in the evaluation of prototype architectures and traffic management algorithms is disclosed. The programmable switch (,) is arranged as an add-on peripheral to a conventional computer system including a host central processing unit (CPU) (,). The switch (,) includes a plurality of port processors (,) in communication with port interfaces (,); each of the port interfaces (,) is a conventional interface for high data rate communication, while the port processors (,) are programmable logic devices. The switch fabric is realized in a multiple slice fashion, by multiple programmable logic devices (,). A central arbiter (,), also realized in programmable logic, controls routing of cells within the switch (,). Programming of the port processors (,), fabric slices (,), and arbiter (,) is effected by downloading, into these devices, bit-streams supplied by the host CPU (,) that define the switch architecture, including selection of input or output queuing and the fabric type, along with the implementation of traffic management algorithms in the port processors (,), fabric slices (,), and arbiter (,). Each of the port processors (,), fabric slices (,), and arbiter (,) also contain memory locations for storing results of operation, which are read by the management port (,) over a management bus (COMET), and may then be forwarded to the host CPU (,), without interfering with switch traffic. The programmable switch (,) is therefore capable of full speed operation as a fast packet switch, thus providing accurate evaluation results.