Semiconductor memory device having bit line precharge circuits activated by separate control signals and control method for the same

Abstract

In a semiconductor memory device which is intended to lower the power consumption and raise the operation speed without increasing the circuit scale to meet trends toward the larger capacity, higher speed and, at the same time, the lower power voltage design, the precharge circuit Pre,has its bit line shorting section formed of transistors TN,A and TN,B in series connection and its bit line voltage holding circuit formed of transistors TN,A and TN,B connected in series between the node of the transistors TN,A and TN,B and a precharge voltage VPR source, with the transistors TN,A and TN,A and the TN,B and TN,B being controlled by precharge signals BRS,and BRS,, respectively. One of the precharge signals BRS,and BRS,is preset active since the former precharge operation cycle, the other precharge signal is activated to start the shorting operation of a bit line pair /BL-BL, and the preset precharge signal is deactivated to end the shorting operation.