The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Dec. 21, 2000
Bruce Lee Inn, San Jose, CA (US);
Alland Chee, Union City, CA (US);
Micrel, Incorporated, San Jose, CA (US);
Abstract
A controller for limiting the current through a pass transistor is described herein that includes an NMOS control transistor coupled between the gate of the pass transistor and ground. The gate of the NMOS control transistor is coupled to a bootstrap circuit via a PMOS transistor. The PMOS transistor is turned on in the event of a current limit signal to momentarily apply the bootstrap voltage to the gate of the NMOS control transistor. This quickly turns on the NMOS control transistor to discharge the gate of the pass transistor, shutting off the pass transistor and terminating the high current situation. After the bootstrapped voltage has been shunted to ground, a reverse biased diode allows the gate of the NMOS control transistor to remain charged to keep the NMOS control transistor on. After the current limit situation has passed, the NMOS control transistor is switched off. Accordingly, short circuits in the load are quickly uncoupled from the remainder of the system by the fast reaction time of the NMOS control transistor.