Gated clock flip-flops

Abstract

A gated scan flop circuit and methods of making the gated scan flop circuit are provided. In one example, the scan flop circuit includes a sub-scan flop circuit that incorporates a multiplexer and a flip flop circuit, and a data terminal D that is connected to the sub-scan flop circuit. Also provided is a first logic gate that is configured to receive a scan input terminal SI and a clock gate terminal G. The first logic gate has a first logic gate output that is connected to the sub-scan flop circuit. A scan enable terminal SE is connected to the sub-scan flip circuit, and a latch circuit is configured to receive the clock gate terminal G, and track its input while the clock terminal CLK is inactive. A second logic gate having a second logic gate output is provided that is configured to receive as inputs the scan enable terminal SE and the latched clock gate terminal G. A third logic gate is configured to receive a clock terminal CLK and the second logic gate output. The third logic gate has a third logic gate output that is connected to the sub-scan flop circuit. The gated scan flop circuit has an output Q and a complementary output /Q. In this example, the first logic gate, the latch circuit, the second logic gate, the third logic gate, and the sub-scan flop circuit are internally integrated circuit components of the scan flop circuit.