The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Sep. 21, 1999
Dimitris C. Pantelakis, Austin, TX (US);
Wai Tong Lau, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
An integrated circuit (,) includes an input buffer circuit (,) having an input stage (,), a delay element (,), inverter (,), and a level shifter (,). The input stage (,) receives an input signal and a first power supply voltage. The level shifter (,) has a pair of cross-coupled P-channel transistors (,and,) coupled to a second power supply voltage. The second power supply voltage is different than the first power supply voltage. The cross-coupled P-channel transistors (,and,) are coupled to first and second N-channel transistors (,and,). Each of the first and second N-channel transistors (,and,) and transistors (,) of the input stage (,) have relatively thick oxide layers. A gate of the first N-channel transistor (,) is coupled to the output of the input stage (,). A gate of the second N-channel transistor (,) is coupled to receive the input signal. The level shifter (,) provides a high speed level shifted output signal at the second power supply voltage level.