The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Jul. 26, 1999
Daniel Claire Baker, Milpitas, CA (US);
Charles Franklin Drill, Boulder Creek, CA (US);
Milind Ganesh Weling, San Jose, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.