The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2001

Filed:

Aug. 17, 1999
Applicant:
Inventors:

Mahjoub Ali Abdelgadir, Orlando, FL (US);

Alvaro Maury, Orlando, FL (US);

Assignee:

Agere Systems Guardian Corp., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/548 ; H01L 2/352 ; H01L 2/940 ;
U.S. Cl.
CPC ...
H01L 2/548 ; H01L 2/352 ; H01L 2/940 ;
Abstract

An integrated circuit includes a conductive layer adjacent a semiconductor substrate. The conductive layer includes conductive lines having gaps therebetween. A fluoro-silicate glass (FSG) layer is over the patterned conductive layer fills the gaps between conductive lines. Also, an undoped oxide layer is on the FSG layer. Peaks of the FSG layer which overlie the conductive metal lines have been reduced by CMP. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.


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Abdelgadir, Mahjoub. (2001). Integrated circuit device having a planar interlevel dielectric layer (U.S. Patent No. 6274933). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6274933

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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