Global planarization method for inter-layer-dielectric and inter-metal dielectric

Abstract

A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material. The planarizing method of the invention has the advantage of not requiring a photolithography step required in a prior art planarization process. In addition, the planarization method of the invention has the advantage of not requiring a process step that subjects an integrated circuit to relatively high temperatures that can have adverse effects on metal conductors present therein.