The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Jun. 23, 2000
Bruce E. White, Jr., Round Rock, TX (US);
Robert Edwin Jones, Jr., Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (,through,). The region (,) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (,). This plug (,) forms a storage node region for a DRAM and electrically contacts to a current electrode (,) of a DRAM pass transistor. Opening (,) is filled concurrently with the filling of opening (,), to form a metallic plug (,) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (,) is filled concurrent with regions (,and,) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (,) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (,through,) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.