The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Jul. 24, 1998
Craig M. Kennedy, San Marcos, CA (US);
Julian Curtis Hart, Round Rock, TX (US);
Fernando J. Ramirez, Fountain Valley, CA (US);
Other;
Abstract
A circuit board interconnect system includes a carrier board with a hybrid solder ball and pin grid array. A plurality of electrically conductive pins extend through the carrier board and are arranged in rows and columns to form a grid array. A first circuit board such as a multi-chip module (MCM) board has a plurality of conductive pads or traces formed on a lower surface thereof that are arranged to form a complementary grid array, i.e. the spacing and location of the conductive pads or traces corresponds to the spacing and location of the pins. A plurality of solder balls are provided with each ball being positioned on top of a corresponding pin so that each solder ball forms a solder connection between a pin and a corresponding conductive pad or trace. A second circuit board such as a computer mother board has a pin connector mounted on an upper surface thereof for individually receiving and providing electrical connection with each of the pins. After reflow, the solder balls wrap around the side walls of the heads of the pins and the side walls of the pads. The resulting generally spherical solder connections are therefore much stronger than conventional elongated fillet connections.