Contingent response apparatus and method for maintaining cache coherency

Abstract

Each processor (,) in a multiple processor system (,) includes a contingent response unit (,). Each contingent response unit (,) includes a pending operation unit (,) for identifying each pending address bus operation from the respective processor which specifies an address matching a snoop address from another processor. A snoop pipeline is associated with the pending operation unit (,) and includes a plurality of pipeline stages (,). Each snoop pipeline stage (,) has a contingent response flag location (,) and an identifier location (,). When a pending operation from the processor specifies an address which is matched by a younger operation from another processor, a contingent response flag control arrangement uses information from the pending operation unit (,) to set a contingent response flag in a first snoop pipeline stage (,). The contingent response flag control also stores in the first snoop pipeline stage (,) an identifier for the matched pending operation. If the matched pending operation finishes the address bus pipeline unsuccessfully and is itself retried, the contingent response flag control arrangement clears the contingent response flag in the snoop pipeline stage (,) in which the flag then resides. Otherwise the contingent response flag is used to provide a snoop response to the younger operation which matched the pending operation.