Non-volatile semiconductor memory device having increased operating speed

Abstract

In order to read a data stored in a given memory cell, two dummy cells are provided, one of which is set to an erase state and the other to a program state. The threshold voltage of each cell attained in the program state is higher than the threshold voltage attained in the erase state and is lower than a maximum read voltage applied between a control gate and a source. Bit lines connected to the drains of the dummy cells are mutually connected through an equalizing switch for generating a reference potential at an intermediate level in a read cycle. The potential of a bit line connected to the drain of the memory cell and the generated reference potential are compared by a differential sense amplifier, so as to sense the state of the memory cell. In this manner, the invention provides a flash memory in which a program operation completed in short time and an accurate read operation can be consistent with each other.