The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2001
Filed:
Dec. 08, 1998
Jun-Ho Sung, Seoul, KR;
Seong-Eun Chung, Seoul, KR;
SamSung Electronics Co., Ltd., Suwon, KR;
Abstract
A liquid crystal display (LCD) interface for communicating a video signal to an LCD comprises a video input device for separating the video signal into a synchronizing signal and R (Red), G (Green) and B (Blue) video signals having a resolution of m rows by n columns, a controller for generating a first clock frequency, a second clock frequency and a third clock frequency being half the second clock frequency based on the synchronizing signal, an R signal converter for dividing the frequency of the R video signal by four according to the first clock frequency to sequentially generate two adjacent pixel column data simultaneously starting both from the first pixel row and the ((m/2)+1),pixel row respectively to the (m/2),pixel row and m,pixel row according to the second clock frequency fo so that the four pixel data arranged in the adjacent pixel columns are simultaneously generated, a G signal converter for dividing the frequency of the G video signal by four according to the first clock frequency to sequentially generate two adjacent pixel column data simultaneously starting both from the first pixel row and the ((m/2)+1),pixel row respectively to the (m/2),pixel row and m,pixel row according to the second clock frequency fo so that the four pixel data arranged in the adjacent pixel columns are simultaneously generated, a B signal converter for dividing the frequency of the B video signal by four according to the first clock frequency to sequentially generate two adjacent pixel column data simultaneously starting both from the first pixel row and the ((m/2)+1),pixel row respectively to the (m/,),pixel row and m,pixel row according to the second clock frequency fo so that the four pixel data arranged in the adjacent pixel columns are simultaneously generated, and an LCD driver for supplying the pixel data from the R, G, B converters to an LCD panel.