The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2001

Filed:

Sep. 01, 1999
Applicant:
Inventor:

Ravindra U. Shenoy, Sunnyvale, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 ;
U.S. Cl.
CPC ...
G05F 1/10 ;
Abstract

A system and method for a supply-independent VCO biasing scheme for generating bias voltages and currents for a VCO of a phase-locked loop are disclosed A biasing scheme for generating a bias electrical signal comprises a first and second current source coupled to a power supply, a current drain coupled to the second current source and to ground, a replica device having a first node, a second node coupled to the second current source and the current drain, and a third node coupled to ground, and a first and second current splitting device having first nodes coupled to each other and to the current source and having third nodes coupled to the first and second nodes of the replica device, respectively.


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