The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2001
Filed:
Sep. 06, 2000
Applicant:
Inventor:
Koichi Itaya, Kanagawa, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/289 ;
U.S. Cl.
CPC ...
H03K 3/289 ;
Abstract
A logic circuit includes a combinational circuit,and a sequential circuit, outputs D,to D,of the combinational circuit,are provided to the respective data inputs D of flip-flops,to,of the sequential circuit through respective multiplexers,to,, and the flip-flops,to,are cascaded through the multiplexers,to,to construct a scan path. AND gates,to,are provided for preventing changes in outputs of the flip-flops,to,from being transmitted to the combinational circuit,when the scan mode signal *SM is active, whereby the combinational circuit,is kept inoperative when data is serially transferred on the scan path consisting of the D flip-flops,to,, an inverter,and the multiplexers,to