The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2001
Filed:
May. 20, 1997
Yasunobu Umemoto, Kanagawa-ken, JP;
Yukinori Uchino, Kanagawa-ken, JP;
Toshikazu Sei, Kanagawa-ken, JP;
Muneaki Maeno, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.