Optimization of ordered stores on a pipelined bus via self-initiated retry

Abstract

Where a plurality of ordered transactions are received for data transfers on a pipelined bus, each transaction in the series is initiated before all prospective retry responses to the preceding ordered transactions may be asserted. The address responses to all preceding ordered transfers are then monitored in connection with performance of the newly initiated transfer. If a retry response to any preceding ordered transaction is asserted, a self-initiated retry response for all subsequent transactions, including the newly initiated transfer, is also asserted. The system-retried transactions and all succeeding, ordered transactions are immediately reattempted. The overlapping performance of the ordered transfers reduces the latency of non-retried transfers, achieving performance comparable to non-ordered transactions. Even where a retry response is asserted, the total latency required for completion of both transactions in the ordered pair is reduced by at least a portion of the address-to-response latency, so that the impact of ordering requirements on system performance is minimized. Strict ordering is thus enforced while taking full advantage of the pipelined nature of the bus to maximize utilization of the bus bandwidth.