Semiconductor memory device for inputting/outputting data through a common terminal and outputting data in synchronism with clock

Abstract

A semiconductor memory device, in which the output is restored to high impedance state and capable of operating always normally even when a prohibited command is input thereto, is disclosed. The device has a common terminal for data input and output, and data are output in synchronism with a clock. The device further comprises an output clock generating circuit for generating a clock in accordance with the output period of the output data, and an output circuit for producing the output data in accordance with the clock. The output clock generating circuit is turned off after generating an additional two cycles of the clock following the end of the production of the output data.