The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2001

Filed:

Jun. 18, 1999
Applicant:
Inventors:

Harumi Kawano, Miyazaki-gun, JP;

Akihiro Sushihara, Miyazaki-gun, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

In addition to first and second control circuits, an I/O circuit has a first MOS transistor which includes a gate electrode connected to a first node to which a first signal is input from at least one of a first power supply and an internal circuit, a first electrode connected to the first power supply, and a second electrode connected to a second node. A second MOS transistor includes a gate electrode connected to a third node, a first electrode, a second electrode connected to a second node, and a substrate connected to a fourth node which is in a floating state. A third MOS transistor includes a gate electrode connected to the third node, a first electrode, a second electrode, and a substrate connected to the fourth node. A fourth MOS transistor includes a gate electrode connected to a fifth node, a first electrode connected to a sixth node to which a signal is either input from an external circuit or from which a signal is output to the external circuit, a second electrode, and a substrate connected to the fourth node. To prevent excess current flow to an output pad, one of the first and second electrodes of the second, third or fourth MOS transistors is in a floating state and is isolated from the fourth node.


Find Patent Forward Citations

Kawano, Harumi. (2001). I/o circuit of semiconductor integrated device (U.S. Patent No. 6269042). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6269042

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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