The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2001

Filed:

Nov. 23, 1999
Applicant:
Inventor:

Christopher Michael Graves, Sherman, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/7687 ;
U.S. Cl.
CPC ...
H03K 1/7687 ;
Abstract

A low voltage CMOS bus switch (,) adapted to connect to a 5V bus (A,B) in a controlled and power-efficient manner. A voltage reference circuit (,) monitors the state of the power supply (Vcc) and provides three control signals (Dref, Dref,, Dref,) when the supply (V,) is powered up or down. These control signals help to keep the switch open when the supply is powered down, and are used in the 5V tolerant circuitry to bias the gates of the pass transistors (MN,,MP,) when the supply is powered up. When the bus voltages are below Vcc, the device operates as a normal low voltage bus switch. As the input voltage increases above Vcc, a P-channel pass transistor (MR,) turns off and a gate voltage of a N-channel pass transistor (MN,) is controlled by the tolerant circuitry. This provides a reliable output signal to either a 3.3V or 5V bus.


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