The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2001
Filed:
Dec. 03, 1999
Applicant:
Inventors:
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/017 ; H03K 5/04 ; H03K 7/08 ;
U.S. Cl.
CPC ...
H03K 3/017 ; H03K 5/04 ; H03K 7/08 ;
Abstract
A Duty cycle optimized prescaler (,) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (,), one (,)to count negative edges of the clock pulse, and one (,)to count positive edges of the clock pulse. Each counter (,) output is connected to a comparator (,) which compares each counter output (,)to a prescaler setting (,). The comparators (,) outputs are input to an OR gate (,), the output of which, when, a logic 1, resets the counters(,) and toggles a flip-flop circuit (,) providing a clock output signal.