The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2001
Filed:
Jan. 11, 2000
Gerald L Esch, Jr., Ft. Collins, CO (US);
Agilent Technologies, Inc., Palo Alto, CA (US);
Abstract
A method and circuit for flattening the output resistance response on a signal pad of an integrated circuit is presented. Impedance matching is accomplished using pull-up and pull-down FET arrays. Various combinations of pull-up PFETs in the pull-up FET array are programmably enabled by a pull-up calibration word when driving the output pad high. Various combinations of pull-down NFETs in the pull-down FET array are programmably enabled by a pull-down calibration word when driving the output pad low. An NFET in the pull-up FET calibration array and a PFET in the pull-down FET array respectively allow the output driver to supply more current during the initial stages of a voltage transition, resulting in a flatter overall output resistance R,response.