The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2001

Filed:

Jun. 30, 1998
Applicant:
Inventors:

Gayle W. Miller, Colorado Springs, CO (US);

Michael F. Chisholm, Garland, TX (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract

A method of fabricating a semiconductor wafer having a polishing endpoint layer which is formed by implanting ions into the wafer includes the step of polishing the wafer in order to remove material from the wafer. The method also includes the step of detecting a first change in friction when material of the ion-implanted polishing endpoint layer begins to be removed during the polishing step. The method further includes the step of detecting a second change in friction when material of the ion-implanted polishing endpoint layer ceases to be removed during the polishing step. Moreover, the method includes the step of terminating the polishing step in response to detection of the second change in friction. An apparatus for polishing a semiconductor wafer down to an ion-implanted polishing endpoint layer in the wafer is also disclosed.


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