The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2001
Filed:
Oct. 27, 1997
Detailed grid point layout using a massively parallel logic including an emulator/simulator paradigm
Applicant:
Inventors:
Richard LaVerne Malm, San Jose, CA (US);
Charles L. Meiley, San Jose, CA (US);
Frank Albert Nemec, II, Saratoga, CA (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method and apparatus for solving grid point layouts using massively parallel computers to solve each wiring connection or grid point independently. By leaving the solution in a global perspective, and solving the problem using fine grain parallelism, wiring solutions and optimized layouts are achieved in a shorter amount of time.