The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2001
Filed:
Jun. 15, 1998
Chau-Shing Hui, Austin, TX (US);
Krishnamurthy Venkatramani, Austin, TX (US);
Barry Joe Wolford, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of providing a value to a cache used in a computer system, by transmitting the value from a system memory device to a lower level (e.g., L2) of the cache using a system bus, acknowledging the forwarding of the address from the lower level of the cache after said transmitting of the value, and acknowledging the forwarding of the address from a higher level (e.g., on-board) of the cache, in response to said transmitting step. The acknowledging of the forwarding of the address from the higher level of the cache, can occur prior to the acknowledgment of the forwarding of the address from the lower level of the cache. The value is transmitted from the lower level of the cache to the higher level of the cache using the higher level bus, in response to said acknowledgement of the forwarding of the address from the higher level of the cache, and this latter transmission can also occur prior to said acknowledgment of the forwarding of the address from the lower level of the cache. This approach results in reduced memory access latency with L2 cache misses, and improves address bus utilization on the higher level bus.