Semiconductor memory device

Abstract

There is provided a non-volatile semiconductor memory device including a memory cell array arranged in a plurality of banks such that while data is erased from or written into one of the banks, data can be read out of one of the rest of the banks, the non-volatile semiconductor memory device including (a) a first switch receiving an external address through an address signal path through which data is to be read out of a first bank, (b) a second switch receiving an external address through an address signal path through which data is to be read out of a second bank, and (c) a latch circuit alternatively receives an external address as an address for writing data or an internal address for erasing data. An address transmitted from the latch circuit is supplied to both the first and second switches. Each of the first and second switches includes an address buffer circuit which transmits a bank address to an address decoder associated with each of the banks in accordance with a control signal transmitted from each of the banks, in dependence on whether each of the banks is in a data-reading operation, a data-writing operation, or a data-erasing operation. The bank address is comprised of an address for reading data, an address for writing data, or an address for erasing data.