The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2001

Filed:

Aug. 31, 2000
Applicant:
Inventors:

Lawrence Lee Aldrich, Colorado Springs, CO (US);

Kim Carver Hardee, Colorado Springs, CO (US);

Assignee:

Mosel Vitelic, Inc., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 ;
U.S. Cl.
CPC ...
G11C 5/06 ;
Abstract

A reduced capacitance architecture for integrated circuits and particularly for memory integrated circuits is disclosed. The integrated circuit has a plurality of levels including first and second levels. A first signal conductor extends within the first level. A second signal conductor also extends within the first level and is positioned adjacent to and in close proximity with the first signal conductor. The second level is positioned adjacent to the first level and includes a third signal conductor extending within it. The third signal conductor is positioned laterally between the first and second conductors to eliminate vertical parallel plate capacitance.


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