The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2001

Filed:

Sep. 10, 1999
Applicant:
Inventors:

Xue-Mei Gong, Austin, TX (US);

Eric Gaalaas, Arlington, MA (US);

Mark Alexander, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 ; H03M 3/00 ;
U.S. Cl.
CPC ...
H03M 1/66 ; H03M 3/00 ;
Abstract

A multi-bit DAC (,) is provided as part of a digital-to-analog data converter (DAC). The multi-bit DAC is comprised of a plurality of single-bit DACs (,) which have the values thereof selected through a digital encoder (,). The digital encoder (,) performs dynamic element matching (DEM) on an input data value. The sequence of selection is performed such that the element mismatch noise response of the DAC (,) is shaped. The outputs are summed at a summing junction (,) and then filtered with a low pass filter (,). In the noise shaping response, a cyclical second order response is provided with a Data Weighted Averaging (DWA) technique wherein the outputs of the DACs are restricted to one of two states. To achieve this, select ones of the output values are changed in order to comply with this restriction, thus deviating from a uniform element selection algorithm. This provides a constrained second order response which accounts for mismatching of the DAC elements (,).


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