Glitch free clock multiplexer circuit

Abstract

A clock selector circuit for selecting a single output clock signal from a multiplicity of input clock signals, each constituted by transitions between binary states, comprises a multiplicity of D-bistables each having a clock input coupled to receive the respective one of the input clock signals, a D-input coupled to receive a hold signal common to the bistables, and an output for providing a respective hold signal. A first multiplexer has inputs coupled to receive the respective input clock signals and is operative to select in response to the selection signal one of said input signals. A second multiplexer has inputs coupled to receive the respective hold signals and is operative to select in response to the selection signal the hold signal corresponding to the clock signal selected by the first multiplexer. A gate is coupled to receive both the clock signal selected by the first multiplexer and the hold signal selected by the second multiplexer and asserts an output whichever of the input signals to the gate may be asserted. The assertion of the common hold signal precedes a chance in state of the selection signal and endures at least until all the hold signals have been asserted and a change in state of the selection signal has occurred. The circuit facilitates glitch-free clock multiplexing.