Dual rail dynamic flip-flop with single evaluation path

Abstract

A dynamic flip-flop circuit that operates in a pre-charge phase and an evaluation phase allows for implementation of multiple-input logic functions without sacrificing performance by using a single evaluation path to generate its output signals. In one embodiment, the dynamic flip-flop circuit includes input logic that receives a clock signal and one or more data input signals. The clock signal defines the pre-charge phase and the evaluation phase of the flip-flop circuit. The input logic has an output terminal connected to a first output buffer circuit, which in turn drives the flip-flop circuit's Q output signal. The output terminal of the input logic is combined with the clock signal in a logic gate having an output terminal connected to a second output buffer circuit, which in turn drives the flip-flop circuit's complementary output signal {overscore (Q)}. During the pre-charge phase, the input logic forces the Q output signal to a first logic state via the first output buffer, and the logic gate forces the {overscore (Q)} output signal to logic low via the second output buffer. During the evaluation phase, the input logic generates a logic signal in response to a predetermined logic function of its one or more input signals. The logic signal(s), in turn, drives the Q output signal via the first output buffer, and drives the {overscore (Q)} output signal to a complementary logic state via the logic gate and second output buffer.