The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2001
Filed:
Nov. 15, 1999
Eiji Hayashi, Tokyo, JP;
Yoshihiro Tomita, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A method for mounting semiconductor elements without lowering the reliability of connection due to the residue of flux in the connection of the semiconductor elements to the wiring substrate. A part of the oxide film of a solder bump,can previously be broken by previously heating a semiconductor element,and a wiring substrate,to a predetermined preheating temperature, and pressure-welding the semiconductor element,to the wiring substrate,. Furthermore, since the oxide film covering the surface of the solder bump,can be absorbed in the solder bump,by rhythmically moving the solder bump in a predetermined direction in the state where the solder bump is melted by heating the solder bump on the semiconductor element and the wiring substrate to a temperature above the melting point of solder, bonding can be performed without using flux. Furthermore, since the surface of the solder bump,formed on the semiconductor element,and/or the wiring substrate,can be prevented from oxidation, or the oxide film can be reduced by the inert gas or reducing gas,in the above-described air isolation box,, the connection between the semiconductor element,and the wiring substrate,can further be stabilized.