The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2001
Filed:
Feb. 20, 1998
Applicant:
Inventor:
Guy Dupenloup, Marly-le-Roi, FR;
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method of translating an integrated circuit chip (IC) design as represented by RTL code to generic netlist using a logic synthesis tool comprising the steps of parsing the RTL code using analyze command of the logic synthesis tool, building the generic netlist using evaluate command of the logic synthesis tool, and recording the generic netlist to a dump file outside the logic synthesis tool. The dump file comprises characteristics of each input ports of current design, characteristics of each output ports of the current design, and characteristics of each cells of the current design.