Microcontroller architecture and associated method providing for testing of an on-chip memory device

Abstract

A microcontroller architecture and an associated method are presented which provide for testing of an “on-chip” memory unit. The microcontroller includes a microcontroller core, the memory unit, a set of input/output (I/O) pads, and an input/output (I/O) pad interface unit, all formed upon a single monolithic semiconductor substrate. The microcontroller core executes instructions and generates data. The memory unit is coupled to the microcontroller core and stores data. The memory unit may include a common static random access memory (SRAM) device having multiple memory cells with load devices permitting static operation. A data latch within the memory unit samples retrieved data and provides the retrieved data to the microcontroller core. The data latch is responsive to a data latch control (DLC) signal produced by the I/O pad interface unit. The I/O pad interface unit receives a signal from one or more members of the set of I/O pads and generates the DLC signal in response to the signal. In a testing mode of the microcontroller, the DLC signal is asserted, and latching of retrieved data occurs on the next transition of a system clock cycle following assertion of the row select signal. Thus in the testing mode, the length of a time period between assertion of the row select signal and the latching of the retrieved data by the data latch is variable and dependent upon the duty cycle of the system clock signal.