Method and apparatus for linking translation lookaside buffer purge operations to cache coherency transactions

Abstract

A method and apparatus link translation lookaside buffer (TLB) purge operations to cache coherency transactions, thereby allowing the TLB purge operations to be performed by hardware without significant software intervention. Computer systems having cache memories associated with multiple cache modules, such as a CPU or an I/O device, typically use a cache coherency protocol to ensure that the cache memories remain consistent with each other and with main memory. Popular cache coherency protocols usually include an INVALIDATE transaction that signals cache memories to invalidate a cache line associated with the address contained in the transaction. A TLB in accordance with the present invention will observe the physical address contained in an INVALIDATE request and determine whether address lies within the page table. If it does, the physical address into the page table will be converted into a virtual page number. The TLB will then be accessed to see if the TLB contains an entry for the virtual page number. If it does, that entry is purged from the TLB. By piggy-backing TLB purges on top of cache coherency transactions, the latency involved with software-based TLB purge operations of the prior art is eliminated. Furthermore, the complexity of the software required to implement the virtual memory scheme is reduced greatly because TLB purge operations are now handled by hardware.