The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2001

Filed:

Dec. 01, 1999
Applicant:
Inventors:

Yutaka Fukutani, Kawasaki, JP;

Tomohiro Nakayama, Kawasaki, JP;

Seizi Hirayama, Kawasaki, JP;

Waichiro Fujieda, Kawasaki, JP;

Arayama Youji, Kawasaki, JP;

Atsushi Fujii, Kawasaki, JP;

Yoshitaka Takahashi, Kawasaki, JP;

Masanori Nagasawa, Kawasaki, JP;

Masakazu Kimura, Kawasaki, JP;

Tutomu Taniguti, Kawasaki, JP;

Hiroyuki Fujimoto, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.


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