The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2001

Filed:

Jul. 06, 1999
Applicant:
Inventors:

Robert E. Stengel, Pompano Beach, FL (US);

Wang-Chang A. Gu, Albuquerque, NM (US);

Gustavo D. Leizerovich, Aventura, FL (US);

Lawrence F. Cygan, Schaumburg, IL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/68 ;
U.S. Cl.
CPC ...
H03F 3/68 ;
Abstract

A power amplifier includes a carrier amplifier path and a peaking amplifier path. The carrier amplifier path includes a carrier amplifier (,), and an impedance transforming network (,). The peaking amplifier path includes a peaking amplifier (,), an impedance transforming network (,), and a phase delay quarter wave element (,). The arrangement forms an inverted Doherty combiner where as the nominal impedance at a summing node (,) increases with increased conduction from the peaking amplifier, the load impedance at the output of the carrier amplifier decreases so as to maintain the carrier amplifier at a saturation point as the input signal (,) increases, and results in a reduction of the number of phase delay elements needed over a conventional Doherty approach. In a preferred embodiment the carrier and peaking amplifiers consist of cascaded stages, and are disposed on a common integrated circuit die (,). The impedance transforming networks and phase delay element are disposed on a common substrate (,), as is an input splitter network (,).


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