The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2001
Filed:
Oct. 08, 1999
Applicant:
Inventors:
Vishnu S. Srinivasan, Austin, TX (US);
John Pacourek, Austin, TX (US);
John James Paulos, Austin, TX (US);
Assignee:
Cirrus Logic, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 ;
U.S. Cl.
CPC ...
G11C 5/14 ;
Abstract
A technique for compensating for supply voltage variations in a delay circuit by utilizing a bias circuit to maintain the delay substantially constant with respect to the supply voltage. The bias circuit generates a bias current having a fixed component and a variable component, in which the variable component varies proportionately to variations in the supply voltage to maintain the delay substantially constant.