The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2001

Filed:

Mar. 10, 1998
Applicant:
Inventors:

Matthias Stecher, Villach, AT;

Tim Gutheit, München, DE;

Werner Schwetlick, Gröbenzell, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 7/18232 ;
U.S. Cl.
CPC ...
H01L 7/18232 ;
Abstract

Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffusion of the further dopant of the second conductivity type, independently of the deep concentration, since the dopant concentration at the surface can be chosen independently of the dopant concentration at depth. A low film resistance results from the great penetration depth of the semiconductor region through the combination of the two dopant profiles. The low film resistance leads to reduced pinching of the substrate current in an NMOS transistor, and to greater stability against “latch-up”, without substantially increasing the concentration of the dopants in the region of source/drain diffusions, and therefore without unfavorably affecting drain/bulk capacitance. In addition, the concentration of the further dopant of the second conductivity type can be kept low. A semiconductor region of a second conductivity type is thus attained which exhibits little outward lateral diffusion. Further, when the components are given the conventional polarity, the semiconductor region is insulated from the p-substrate by the buried zone.


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