The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2001
Filed:
Feb. 11, 2000
Jung Ho Lee, Seoul, KR;
Seung Chul Lee, Kyungki-do, KR;
Noh Yeal Kwak, Kyungki-do, KR;
In Seok Yeo, Kyungki-do, KR;
Sahng Kyoo Lee, Seoul, KR;
Hyundai Electronics Industries Co., Ltd., Kyungki-do, KR;
Abstract
The present invention relates to a method of manufacturing a junction in a semiconductor device. When forming an elevated source/drain junction (ESD) of a buried channel field effect transistor (BC-FET) using a selective epitaxial growth (SEG) technique, a self-aligned epitaxial silicon (SESS) is formed on the lower portion of a gate side-wall spacer, resulting in the improvement of a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (EDS) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as the increase of the current density by lowering the series resistance of source/drain extension.