The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2001
Filed:
Sep. 14, 1999
Takashi Fujikawa, Kashima, JP;
Masaharu Ninomiya, Saga Prefecture, JP;
Sumitomo Metal Industries, Ltd., Osaka, JP;
Abstract
The objective of this invention is to provide a manufacturing method wherewith optimally low-COP substrates can be efficiently manufactured for epitaxial wafers in order to obtain high epitaxial surface quality that will not have an adverse effect on device characteristics. A phenomenon was discovered whereby COPs are eliminated by solution annealing or flattening when epitaxial films are formed on wafers wherein the density of grown-in defects (COPs) with a size of 0.130 &mgr;m or larger is 0.03 defects/cm,or lower, the use of which phenomenon is characteristic of the invention. For example, by pulling a monocrystal while deliberately controlling the carbon concentration therein to within a prescribed high range, and employing wafers cut from silicon monocrystal ingots grown with a pulling speed wherewith no OSF-ring outer region is present in the wafer surface, wafers having the low COP densities noted above are obtained, and the COPs are eliminated by solution-annealing or flattening when forming the epitaxial film, wherefore high-quality epitaxial wafers can be manufactured with good yield.