The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2001

Filed:

Oct. 20, 1998
Applicant:
Inventors:

Thomas C. Brennan, Rochester, MN (US);

Michael Rohn, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A system and method for designing an integrated circuit device by selectively reducing power lines based on wiring demand of the device are provided. In one embodiment, a power demand value of a region of the device is determined and a wiring demand value of the region of the device is determined. Based on the wiring demand value and the power demand Value, power lines in the region are selectively reduced. These steps may be repeated for each region of the device and a new power line layout may be generated after stepping through each of the regions. The reduction of power lines may be repeated until an acceptable power line layout is produced. Based on this layout, detailed signal wiring can be performed. This technique can, for example, more efficiently allocate power lines and signal wires and increase the density of the integrated circuit chip.


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